山东大学EDA第二次硬件实验

实验任务一：七段译码器（共阳极）

【实验代码】

七人表决：

library ieee;

use ieee.std_logic_1164.all;

entity vote is

port(a:in std_logic_vector(6 downto 0);

y:out std_logic);

end vote;

architecture info of vote is

begin process(a)

variable i:integer;

begin i:=0;

if(a(0)='1') then i:=i+1;

end if;

if(a(1)='1') then i:=i+1;

end if;

if(a(2)='1') then i:=i+1;

end if;

if(a(3)='1') then i:=i+1;

end if;

if(a(4)='1') then i:=i+1;

end if;

if(a(5)='1') then i:=i+1;

end if;

if(a(6)='1') then i:=i+1;

end if;

if(i>3)

then y<='1';

else y<='0';

end if;

end process;

end info;

实验任务二：八位二进制加法器

【实验代码】

Add_8:

LIBRARY IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity add_8 IS

port (A: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

B: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

CIN: IN STD_LOGIC;

SUM:out std_logic_vector(7 downto 0);

COUT: OUT STD_LOGIC);

end add_8;

ARCHITECTURE info OF add_8 IS

COMPONENT add_4

port(a,b:in std_logic_vector(3 downto 0);

cin:in std_logic;

cout:out std_logic;

sum:out std_logic_vector(3 downto 0));

END COMPONENT;

signal SC:std_logic;

begin

U1:add_4

port map(cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),cout=>sc,sum=>sum(3 downto 0));

U2:add_4

port map(cin=>sc,a=>a(7 downto 4),b=>b(7 downto 4),cout=>cout,sum=>sum(7 downto 4));

END ARCHITECTURE info;

Add_4 U1:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity add_4 is

port(a,b:in std_logic_vector(3 downto 0);

cin:in std_logic;

cout:out std_logic;

sum:out std_logic_vector(3 downto 0));

end entity add_4;

architecture info of add_4 is

signal data:std_logic_vector(4 downto 0);

begin

data<=('0'& a)+('0' & b)+("0000" & cin);

cout<=data(4);

sum<=data(3 downto 0);

end info;

Add4:U2

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